This invention pertains to Direct Sequence Code Division Multiple Access (DS-CDMA) technology. More particularly this invention pertains to a DS-CDMA receiver and method for synchronizing the DS-CDMA receiver, and a communication system in which the DS-CDMA receiver is used.
Direct Sequence Code Division Multiple Access (DS-CDMA) has emerged as the preeminent method for sharing a spectrum allocation among a plurality of communication channels, e.g., a plurality of wireless devices using a wireless network cell. DS-CDMA has been proven in practice to offer higher data rates for a given bandwidth allocation than competing systems, e.g., Time Division Multiple Access (TDMA) or frequency hopping spread spectrum.
DS-CDMA is also a type of spread spectrum signaling method. As opposed to frequency hopping spread spectrum techniques, a DS-CDMA signal uses an entire allocated bandwidth at any given instant.
In the DS-CDMA signaling method a binary data sequence, which is biased so that two equal signal states correspond to equal and opposite sign signal levels, is multiplied by a DS-CDMA code which is biased in the same manner, but is characterized by a much higher frequency. For example, every bit cycle of the binary data sequence typically corresponds to from 7 to 127 signal periods of the DS-CDMA code. The signal periods of the DS-CDMA code are referred to as chips. The DS-CDMA code can comprise a pseudo random number sequence or a Walsh code. The DS-CDMA code is repeatedly multiplied by successive bits of the binary data sequence. Each communication channel has a unique DS-CDMA code for the purpose of discrimination. The product of the data sequence and the DS-CDMA code can be used to modulate a carrier frequency in a binary phase shift key (BPSK) modulator to produce an RF signal for transmission.
At a receiver a RF to baseband demodulator is used to demodulate the received RF signal. An output of the RF to baseband demodulator is filtered by a low pass filter to produce a filtered signal. The filtered signal comprises the aforementioned product also know as a baseband signal plus noise and interference. A bit demodulator then multiplies the baseband signal by a locally stored copy of the DS-CDMA code. If in performing the multiplication, the locally stored DS-CDMA code is properly temporally aligned with the received baseband signal, then the two instances of the DS-CDMA code (the one by which the data sequence is multiplied in the transmitter, and the one by which the demodulated base band signal is multiplied in the receiver) will multiply out to unity leaving the original binary data sequence.
A challenge in DS-CDMA technology is the proper temporal alignment of the locally stored DS-CDMA code with the DS-CDMA code in the received baseband signal.
One prior art approach is to transmit a predefined training signal based on a sequence of DS-CDMA codes that are not multiplied by a binary data sequence. After RF-to baseband demodulation, and filtering successive bit length (DS-CDMA code sequence length) vectors are extracted from the baseband signal by sampling it with an analog to digital converter. The corresponding chip complex values in the vectors are averaged to produce an average vector. The averaging operation serves to reduce random noise. A cross correlation calculation is then performed at various relative shifts (the relative shifts can be cyclical shifts of the vector. In a cyclical shift each element is advanced by one position and the last element is moved to the first element positions or vice versa depending on the direction of the shift) between the average vector and the DS-CDMA code sequence which is stored in the receiver in order to determine a correct shift between the received signal and the DS-CDMA code stored in memory (in a predetermined shift state). The correct shift information can then be used to properly synchronize the receiver with the baseband signal, e.g., by shifting by the correct shift points in the baseband signal at which the successive chip complex values of the DS-CDMA code are multiplied.
According to another technique, rather than sending a signal based on a sequence of DS-CDMA codes that are not multiplied by a binary data sequence, a signal is sent which is based on multiplying the DS-CDMA code by a training sequence which is also stored in the receiver. In the receiver the DS-CDMA code is multiplied by successive bits in the training sequence, and the process continues in similar fashion to the process discussed in the foregoing paragraph.
Both of these methods for synchronizing a DS-CDMA receiver to a received baseband signal suffer from the drawback that a training period during which data cannot be transmitted is necessitated. This diminishes an average data rate at which the receiver can receive information.
The problem of synchronizing a DS-CDMA receiver to baseband signal is exacerbated by the fact that DS-CDMA signals are spread over a large bandwidth and are close to the noise floor of communication systems in which they are used.
Noise problems can be overcome to an extent by averaging over more bit length vectors during the synchronization. However, to do so would require extending the training period to receive more bit length vectors. Extending the training time would further diminish the average data rate.
DS-CDMA receivers utilize an oscillator, usually a crystal based oscillator to generate a master clock signal. The master clock signal is used after dividing down, for clocking the sampling times of the analog to digital converter and timing the multiplication of the baseband signal by the DS-CDMA code in the bit demodulator. The master clock signal is also used to generate a local oscillator signal used in the RF to baseband demodulator. Low cost oscillators can cause errors in the master clock signal and signals derived therefrom. Additionally environmental factors such as Doppler fading can also lead to discrepancies between the frequencies of signals derived from the master clock signal and frequencies of the received signal (e.g., carrier frequency, bit rate). It would be desirable to use lower cost oscillators (e.g., based on lower cost crystals), but to do so would necessitate more frequent synchronization training periods which would further reduce the average data rate.
In the interest of conserving a receiver""s battery power, it would be desirable to only obtain 1 sample per chip, however to do so would be detrimental to a signal to noise ratio, unless the sample timing is aligned near a center (peak) of a chip pulse shape function of the baseband signal. If a lower cost oscillator is used, unless the receiver is frequently synchronized, which would result in a lower data rate in the case of the prior art methods mentioned above, the sample timing will drift off alignment causing a reduction in the signal to noise ratio, and perforce data errors.
Presently, the cost of crystal oscillators presents a cost reduction barrier for wireless communication devices.
What is needed is a system and method for maintaining the synchronization of a DS-CDMA receiver, without compromising the average data rate.
What is needed is a system and method for maintaining the synchronization of a DS-CDMA receiver having a low precision oscillator without compromising the data rate.
What is needed is a system and method for maintaining the synchronization of a DS-CDMA receiver operating in a noisy environment without compromising the data rate.